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| ae0.1e fujitsu semiconductor data sheet advanced info. memory cmos 4 512 k 32 bit synchronous dynamic ram mb81f643242c-60/-70/-10 cmos 4-bank 524,288-word 32 bit synchronous dynamic random access memory n description the fujitsu mb81f643242c is a cmos synchronous dynamic random access memory (sdram) containing 67,108,864 memory cells accessible in a 32-bit format. the mb81f643242c features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. the mb81f643242c sdram is designed to reduce the complexity of using a standard dynamic ram (dram) which requires many control signal timing constraints, and may improve data bandwidth of memory as much as 5 times more than a conventional dram. the mb81f643242c is ideally suited for workstations, personal computers, laser printers, high resolution graphic adapters/accelerators and other applications where an extremely large memory and bandwidth are required and where a simple interface is needed. n product line & features parameter mb81f643242c reference value@ 67 mhz, cl = 3 -60 -70 -10 cl - t rcd - t rp cl = 2 2 - 2 - 2 clk min. 2 - 2 - 2 clk min. 2 - 2 - 2 clk min. 2 - 2 - 2 clk min. cl = 3 3 - 3 - 3 clk min. 3 - 3 - 3 clk min. 3 - 3 - 3 clk min. 3 - 3 - 3 clk min. clock frequency 167 mhz max. 143 mhz max. 100 mhz max. 67 mhz max. burst mode cycle time cl = 2 10 ns min. 10 ns min. 15 ns min. 20 ns min. cl = 3 6 ns min. 7 ns min. 10 ns min. 15 ns min. access time from clock cl = 2 6 ns max. 6 ns max. 7 ns max. 7 ns max. cl = 3 5.5 ns max. 5.5 ns max. 7 ns max. 7 ns max. operating current 165 ma max. 155 ma max. 115 ma max. 100 ma max. power down mode current (i cc2p ) 2 ma max. self refresh current (i cc6 ) 2 ma max. ? single +3.3 v supply 0.3 v tolerance ? lvttl compatible i/o interface ? 4 k refresh cycles every 64 ms ? four bank operation ? burst read/write operation and burst read/single write operation capability ? programmable burst type, burst length, and cas latency ? auto-and self-refresh (every 15.6 m s) ? cke power down mode ? output enable and input data mask
2 mb81f643242c-60/-70/-10 advanced info (ae0.1e) n package package and ordering information C 86-pin plastic (10.16 22.22 mm) tsop-ii without scitt function, order as mb81f643242c- fn C 86-pin plastic (10.16 22.22 mm) tsop-ii with scitt function, order as mb81f643242c- fn-s 86 pin plastic tsop(ii) package (fpt-86p-m01) (normal bend) 3 mb81f643242c-60/-70/-10 advanced info (ae0.1e) n pin assignments and descriptions 86-pin tsop(ii) (top view) 4 mb81f643242c-60/-70/-10 advanced info (ae0.1e) pin number symbol function 1, 3, 9, 15, 29, 35, 41, 43, 49, 55, 75, 81 v cc , v ccq supply voltage 2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36, 37, 39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56, 74, 76, 77, 79, 80, 82, 83, 85 dq 0 to dq 31 data i/o 6, 12, 32, 38, 44, 46, 52, 58, 72, 78, 84, 86 v ss , v ssq ground 14, 21, 30, 57, 69, 70, 73 n.c. no connection 17 we write enable 18 cas column address strobe 19 ras row address strobe 20 cs chip select 22, 23 ba 1 , ba 0 bank select (bank address) 24 ap auto precharge enable 24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66 a 0 to a 10 address input ? row: a 0 to a 10 ? column: a 0 to a 7 67 cke clock enable 68 clk clock input 16, 28, 59, 71 dqm 0 to dqm 3 input mask/output enable 5 mb81f643242c-60/-70/-10 advanced info (ae0.1e) n block diagram fig. 1 C mb81f643242c block diagram bank-1 v cc v ss clk cke a 0 to a 9 , a 10 /ap dq 0 to dq 31 command decoder clock buffer address buffer/ register i/o data buffer/ register mode register ras cas we dram core (2,048 256 32) col. addr. ras cas we cs bank-0 i/o row addr. to each block control signal latch v ccq bank-2 bank-3 ba 1 ba 0 column address counter dqm 0 to dqm 3 v ssq 6 mb81f643242c-60/-70/-10 advanced info (ae0.1e) n functional truth table note *1 command truth table note *2, *3, and *4 notes: *1. v = valid, l = logic low, h = logic high, x = either l or h. *2. all commands assumes no csus command on previous rising edge of clock. *3. all commands are assumed to be valid state transitions. *4. all inputs are latched on the rising edge of clock. *5. nop and desl commands have the same effect on the part. unless specifically noted, nop will represent both nop and desl command in later descriptions. *6. read, reada, writ and writa commands should only be issued after the corresponding bank has been activated (actv command). refer to state diagram in section n functional description. *7. actv command should only be issued after corresponding bank has been precharged (pre or pall command). *8. required after power up. *9. mrs command should only be issued after all banks have been precharged (pre or pall command). refer to state diagram in section n functional description. function notes symbol cke cs ras cas we ba 1 , ba 0 a 10 (ap) a 9 to a 8 a 7 to a 0 n-1 n device deselect *5 desl h x h x x x x x x x no operation *5 nop h x l h h h x x x x burst stop bst h x l h h l x x x x read *6 read h x l h l h v l x v read with auto-precharge *6 reada h x l h l h v h x v write *6 writ h x l h l l v l x v write with auto-precharge *6 writa h x l h l l v h x v bank active *7 actv h x l l h h v v v v precharge single bank pre h x l l h l v l x x precharge all banks pall h x l l h l x h x x mode register set *8, *9 mrs h x l l l l l l v v 7 mb81f643242c-60/-70/-10 advanced info (ae0.1e) dqm truth table notes: *1. i = 0, 1, 2, 3 *2. dqm 0 for dq 0 to dq 7 , dqm 1 for dq 8 to dq 15 , dqm 2 for dq 16 to dq 23 , dqm 3 for dq 24 to dq 31 , cke truth table notes: *1. the csus command requires that at least one bank is active. refer to state diagram in section n functional description. nop or dsel commands should only be issued after csus and pre(or pall) commands asserted at the same time. *2. ref and self commands should only be issued after all banks have been precharged (pre or pall command). refer to state diagram in section n functional description. *3. self and pd commands should only be issued after the last read data have been appeared on dq. *4. cke should be held high within one t rc period after t cksp . function symbol cke dqmi *1, *2 n-1 n data write/output enable enbi *1 hx l data mask/output disable maski *1 hx h current state function notes symbol cke cs ras cas we ba 1 , ba 0 a 10 (ap) a 9 to a 0 n-1 n bank active clock suspend mode entry *1 csus h l x x x x x x x any (except idle) clock suspend continue *1 l l x x x x x x x clock suspend clock suspend mode exit l h x x x x x x x idle auto-refresh command *2 ref h h l l l h x x x idle self-refresh entry *2, *3 self h l l l l h x x x self refresh self-refresh exit *4 selfx lh l h h h x x x lhh x x x x x x idle power down entry *3 pd hl l h h h x x x hl h x x x x x x power down power down exit lh l h h h x x x lhh x x x x x x 8 mb81f643242c-60/-70/-10 advanced info (ae0.1e) operation command table (applicable to single bank) (continued) current state cs ras cas we addr command function notes idle h x x x x desl nop lhhh x nop nop lhhl x bst nop l h l h ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv bank active after t rcd l l h l ba, ap pre/pall nop l l l h x ref/self auto-refresh or self-refresh *3, *6 llll mode mrs mode register set (idle after t rsc ) *3, *7 bank active h x x x x desl nop lhhh x nop nop lhhl x bst nop l h l h ba, ca, ap read/reada begin read; determine ap l h l l ba, ca, ap writ/writa begin write; determine ap l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall precharge; determine precharge type l l l h x ref/self illegal l l l l mode mrs illegal 9 mb81f643242c-60/-70/-10 advanced info (ae0.1e) (continued) (continued) current state cs ras cas we addr command function notes read hxxx x desl nop (continue burst to end ? bank active) lhhh x nop nop (continue burst to end ? bank active) l h h l x bst burst stop ? bank active l h l h ba, ca, ap read/reada terminate burst, new read; determine ap l h l l ba, ca, ap writ/writa terminate burst, start write; determine ap *4 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall terminate burst, precharge ? idle; determine precharge type l l l h x ref/self illegal l l l l mode mrs illegal write hxxx x desl nop (continue burst to end ? bank active) lhhh x nop nop (continue burst to end ? bank active) l h h l x bst burst stop ? bank active l h l h ba, ca, ap read/reada terminate burst, start read; determine ap *4 l h l l ba, ca, ap writ/writa terminate burst, new write; determine ap l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall terminate burst, precharge; determine precharge type l l l h x ref/self illegal l l l l mode mrs illegal 10 mb81f643242c-60/-70/-10 advanced info (ae0.1e) (continued) (continued) current state cs ras cas we addr command function notes read with auto- precharge hxxx x desl nop (continue burst to end ? precharge ? idle) lhhh x nop nop (continue burst to end ? precharge ? idle) l h h l x bst illegal l h l h ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall illegal *2 l l l h x ref/self illegal l l l l mode mrs illegal write with auto- precharge hxxx x desl nop (continue burst to end ? precharge ? idle) lhhh x nop nop (continue burst to end ? precharge ? idle) l h h l x bst illegal l h l h ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall illegal *2 l l l h x ref/self illegal l l l l mode mrs illegal 11 mb81f643242c-60/-70/-10 advanced info (ae0.1e) (continued) (continued) current state cs ras cas we addr command function notes pre- charging h x x x x desl nop (idle after t rp ) l h h h x nop nop (idle after t rp ) l h h l x bst nop (idle after t rp ) l h l h ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall nop (pall may affect other bank) *5 l l l h x ref/self illegal l l l l mode mrs illegal bank activating h x x x x desl nop (bank active after t rcd ) l h h h x nop nop (bank active after t rcd ) l h h l x bst nop (bank active after t rcd ) l h l h ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall illegal *2 l l l h x ref/self illegal l l l l mode mrs illegal 12 mb81f643242c-60/-70/-10 advanced info (ae0.1e) (continued) abbreviations: ra = row address ba = bank address ca = column address ap = auto precharge notes: *1. all entries in operation command table assume the cke was high during the proceeding clock cycle and the current clock cycle. illegal means dont used command. if used, power up sequence be asserted after power shut down. *2. illegal to bank in specified state; entry may be legal in the bank specified by ba, depending on the state of that bank. *3. illegal if any bank is not idle. *4. must satisfy bus contention, bus turn around, and/or write recovery requirements. refer to timing diagram -11 & -12 in section n timing diagrams. *5. nop to bank precharging or in idle state. may precharge bank specified by ba (and ap). *6. self command should only be issued after the last read data have been appeared on dq. *7. mrs command should only be issued on condition that all dq are in hi-z. current state cs ras cas we addr command function notes refreshing h x x x x desl nop (idle after t rc ) l h h x x nop/bst nop (idle after t rc ) lhlx x read/reada/ writ/writa illegal llhx x actv/ pre/pall illegal lllx x ref/self/ mrs illegal mode register setting h x x x x desl nop (idle after t rsc ) l h h h x nop nop (idle after t rsc ) l h h l x bst illegal lhlx x read/reada/ writ/writa illegal llxx x actv/pre/ pall/ref/ self/mrs illegal 13 mb81f643242c-60/-70/-10 advanced info (ae0.1e) command truth table for cke note *1 (continued) current state cke n-1 cke n cs ras cas we addr function notes self- refresh hxxxxx x invalid lhhxxx x exit self-refresh (self-refresh recovery ? idle after t rc ) lhlhhh x exit self-refresh (self-refresh recovery ? idle after t rc ) l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain self-refresh) self- refresh recovery lxxxxx x invalid h h h x x x x idle after t rc h h l h h h x idle after t rc h h l h h l x illegal h h l h l x x illegal h h l l x x x illegal hhxxxx x illegal hlxxxx x illegal *2 14 mb81f643242c-60/-70/-10 advanced info (ae0.1e) (continued) (continued) current state cke n-1 cke n cs ras cas we addr function notes power down hxxxxx x invalid lhhxxx x exit power down mode ? idle lhlhhh x l l x x x x x nop (maintain power down mode) l h l l x x x illegal l h l h l x x illegal all banks idle hhhxxx mode refer to the operation command table. hhlhxx mode refer to the operation command table. hhl lhx mode refer to the operation command table. h h l l l h x auto-refresh hhllll mode refer to the operation command table. h l h x x x x power down h l l h h h x power down hllhhl x illegal h l l h l x x illegal h l l l h x x illegal h l l l l h x self-refresh *3 hlllll x illegal lxxxxx x invalid 15 mb81f643242c-60/-70/-10 advanced info (ae0.1e) (continued) notes: *1. all entries in command truth table for cke are specified at cke(n) state and cke input from cke(n-1) to cke(n) state must satisfy corresponding set up and hold time for cke. *2. cke should be held high for t rc period. *3. self command should only be issued after the last data have been appeared on dq. current state cke n-1 cke n cs ras cas we addr function notes bank active, bank activating, read/write hhxxxx x refer to the operation command table. h l x x x x x begin clock suspend next cycle lxxxxx x invalid clock suspend hxxxxx x invalid l h x x x x x exit clock suspend next cycle l l x x x x x maintain clock suspend any state other than listed above lxxxxx x invalid hhxxxx x refer to the operation command table. h l x x x x x illegal 16 mb81f643242c-60/-70/-10 advanced info (ae0.1e) n functional description sdram basic function three major differences between this sdram and conventional drams are: synchronized operation, burst mode, and mode register. the synchronized operation is the fundamental difference. an sdram uses a clock input for the synchronization, where the dram is basically asynchronous memory although it has been using two clocks, ras and cas . each operation of dram is determined by their timing phase differences while each operation of sdram is determined by commands and all operations are referenced to a positive clock edge. fig. 2 shows the basic timing diagram differences between sdrams and drams. the burst mode is a very high speed access mode utilizing an internal column address generator. once a column addresses for the first access is set, following addresses are automatically generated by the internal column address counter. the mode registe r is to justify the sdram operation and function into desired system conditions. mode register table shows how sdram can be configured for system requirement by mode register programming. clock input (clk) and clock enable (cke) all input and output signals of sdram use register type buffers. a clk is used as a trigger for the register and internal burst counter increment. all inputs are latched by a positive edge of clk. all outputs are validated by the clk. cke is a high active clock enable signal. when cke = low is latched at a clock input during active cycle, the next clock will be internally masked. during idle state (all banks have been precharged), the power down mode (standby) is entered with cke = low and this will make extremely low standby current. chip select (cs ) cs enables all commands inputs, ras , cas , and we , and address input. when cs is high, command signals are negated but internal operation such as burst cycle will not be suspended. if such a control isnt needed, cs can be tied to ground level. command input (ras , cas and we ) unlike a conventional dram, ras , cas , and we do not directly imply sdram operation, such as row address strobe by ras . instead, each combination of ras , cas , and we input in conjunction with cs input at a rising edge of the clk determines sdram operation. refer to n functional truth table. address input (a 0 to a 10 ) address input selects an arbitrary location of a total of 524,288 words of each memory cell matrix. a total of nineteen address input signals are required to decode such a matrix. sdram adopts an address multiplexer in order to reduce the pin count of the address line. at a bank active command (actv), eleven row addresses are initially latched and the remainder of eight column addresses are then latched by a column address strobe command of either a read command (read or reada) or write command (writ or writa). bank select (ba 0 , ba 1 ) this sdram has four banks and each bank is organized as 512 k words by 32-bit. bank selection by ba 0 , ba 1 occurs at bank active command (actv) followed by read (read or reada), write (writ or writa), and precharge command (pre). 17 mb81f643242c-60/-70/-10 advanced info (ae0.1e) data input and output (dq 0 to dq 31 ) input data is latched and written into the memory at the clock following the write command input. data output is obtained by the following conditions followed by a read command input: t rac ; from the bank active command when t rcd (min) is satisfied. (this parameter is reference only.) t cac ; from the read command when t rcd is greater than t rcd (min). (this parameter is reference only.) t ac ; from the clock edge after t rac and t cac . the polarity of the output data is identical to that of the input. data is valid between access time (determined by the three conditions above) and the next positive clock edge (t oh ). data i/o mask (dqm) dqm is an active high enable input and has an output disable and input mask function. during burst cycle and when dqm 0 to dqm 3 = high is latched by a clock, input is masked at the same clock and output will be masked at the second clock later while internal burst counter will increment by one or will go to the next stage depending on burst type. dqm 0 , dqm 1, dqm 2 , dqm 3 , controls dq 0 to dq 7, dq 8 to dq 15, dq 16 to dq 23, dq 24 to dq 31, respectively. burst mode operation and burst type the burst mode provides faster memory access. the burst mode is implemented by keeping the same row address and by automatic strobing column address. access time and cycle time of burst mode is specified as t ac and t ck , respectively. the internal column address counter operation is determined by a mode register which defines burst type and burst count length of 1, 2, 4 or 8 bits of boundary. in order to terminate or to move from the current burst mode to the next stage while the remaining burst count is more than 1, the following combinations will be required: the burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. the sequential mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant address (= 0). the interleave mode is a scrambled decoding scheme for a 0 and a 2 . if the first access of column address is even (0), the next address will be odd (1), or vice-versa.when the full burst operation is executed at single write mode, auto-precharge command is valid only at write operation. the burst type can be selected either sequential or interleave mode. but only the sequential mode is usable to the full column burst. the sequential mode is an incremental decoding scheme within a boundary address to be determined by burst length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant address (= 0). current stage next stage method (assert the following command) burst read burst read read command burst read burst write 1st step mask command (normally 3 clock cycles) 2nd step write command after l owd burst write burst write write command burst write burst read read command burst read precharge precharge command burst write precharge precharge command 18 mb81f643242c-60/-70/-10 advanced info (ae0.1e) full column burst and burst stop command (bst) the full column burst is an option of burst length and available only at sequential mode of burst type. this full column burst mode is repeatedly access to the same column. if burst mode reaches end of column address, then it wraps round to first column address (= 0) and continues to count until interrupted by the news read (read) /write (writ), precharge (pre), or burst stop (bst) command. the selection of auto-precharge option is illegal during the full column burst operation except write command at burst read & single write mode. the bst command is applicable to terminate the burst operation. if the bst command is asserted during the burst mode, its operation is terminated immediately and the internal state moves to bank active. when read mode is interrupted by bst command, the output will be in high-z. for the detail rule, please refer to timing diagram - 8 in section n timing diagrams. when write mode is interrupted by bst command, the data to be applied at the same time with bst command will be ignored. burst read & single write the burst read and single write mode provides single word write operation regardless of its burst length. in this mode, burst read operation does not be affected by this mode. burst length starting column address a 2 a 1 a 0 sequential mode interleave 2 x x 0 0 C 1 0 C 1 x x 1 1 C 0 1 C 0 4 x 0 0 0 C 1 C 2 C 3 0 C 1 C 2 C 3 x 0 1 1 C 2 C 3 C 0 1 C 0 C 3 C 2 x 1 0 2 C 3 C 0 C 1 2 C 3 C 0 C 1 x 1 1 3 C 0 C 1 C 2 3 C 2 C 1 C 0 8 0 0 0 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 0 0 1 1 C 2 C 3 C 4 C 5 C 6 C 7 C 0 1 C 0 C 3 C 2 C 5 C 4 C 7 C 6 0 1 0 2 C 3 C 4 C 5 C 6 C 7 C 0 C 1 2 C 3 C 0 C 1 C 6 C 7 C 4 C 5 0 1 1 3 C 4 C 5 C 6 C 7 C 0 C 1 C 2 3 C 2 C 1 C 0 C 7 C 6 C 5 C 4 1 0 0 4 C 5 C 6 C 7 C 0 C 1 C 2 C 3 4 C 5 C 6 C 7 C 0 C 1 C 2 C 3 1 0 1 5 C 6 C 7 C 0 C 1 C 2 C 3 C 4 5 C 4 C 7 C 6 C 1 C 0 C 3 C 2 1 1 0 6 C 7 C 0 C 1 C 2 C 3 C 4 C 5 6 C 7 C 4 C 5 C 2 C 3 C 0 C 1 1 1 1 7 C 0 C 1 C 2 C 3 C 4 C 5 C 6 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 19 mb81f643242c-60/-70/-10 advanced info (ae0.1e) precharge and precharge option (pre, pall) sdram memory core is the same as conventional drams, requiring precharge and refresh operations. precharge rewrites the bit line and to reset the internal row address line and is executed by the precharge command (pre). with the precharge command, sdram will automatically be in standby state after precharge time (t rp ). the precharged bank is selected by combination of ap and ba 0 , ba 1 when precharge command is asserted. if ap = high, all banks are precharged regardless of ba 0 , ba 1 (pall). if ap = low, a bank to be selected by ba 0 , ba 1 is precharged (pre). the auto-precharge enters precharge mode at the end of burst mode of read or write without precharge command assertion. this auto precharge is entered by ap = high when a read or write command is asserted. refer to n functional truth table. auto-refresh (ref) auto-refresh uses the internal refresh address counter. the sdram auto-refresh command (ref) generates precharge command internally. all banks of sdram should be precharged prior to the auto-refresh command. the auto-refresh command should also be asserted every 16 m s or a total 4096 refresh commands within a 64 ms period. self-refresh entry (self) self-refresh function provides automatic refresh by an internal timer as well as auto-refresh and will continue the refresh function until cancelled by selfx. the self-refresh is entered by applying an auto-refresh command in conjunction with cke = low (self). once sdram enters the self-refresh mode, all inputs except for cke will be dont care (either logic high or low level state) and outputs will be in a high-z state. during a self-refresh mode, cke = low should be maintained. self command should only be issued after last read data has been appeared on dq notes: when the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted prior to the self-refresh mode entry. self-refresh exit (selfx) to exit self-refresh mode, apply minimum t cksp after cke brought high, and then the no operation command (nop) or the deselect command (desl) should be asserted within one t rc period. cke should be held high within one t rc period after t cksp . refer to timing diagram -16 in section n timing diagrams for the detail. it is recommended to assert an auto-refresh command just after the t rc period to avoid the violation of refresh period. notes: when the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted after the self-refresh exit. mode register set (mrs) the mode register of sdram provides a variety of different operations. the register consists of four operation fields; burst length, burst type, cas latency, and operation code. refer to n mode register table. the mode register can be programmed by the mode register set command (mrs). each field is set by the address line. once a mode register is programmed, the contents of the register will be held until re-programmed by another mrs command (or part loses power). mrs command should only be issued on condition that all dq is in hi-z. the condition of the mode register is undefined after the power-up stage. it is required to set each field after initialization of sdram. refer to power-up initialization below. 20 mb81f643242c-60/-70/-10 advanced info (ae0.1e) power-up initialization the sdram internal condition after power-up will be undefined. it is required to follow the following power on sequence to execute read or write operation. 1. apply power and start clock. attempt to maintain either nop or desl command at the input. 2. maintain stable power, stable clock, and nop condition for a minimum of 100 m s. 3. precharge all banks by precharge (pre) or precharge all command (pall). 4. assert minimum of 2 auto-refresh command (ref). 5. program the mode register by mode register set command (mrs). in addition, it is recommended dqm and cke to track v cc to insure that output is high-z state. the mode register set command (mrs) can be set before 2 auto-refresh command (ref). 21 mb81f643242c-60/-70/-10 advanced info (ae0.1e) cas latency = 2 ras cas clk cs t si ras cas we burst length = 4 active read/write precharge 22 mb81f643242c-60/-70/-10 advanced info (ae0.1e) mode register set self refresh idle read suspend bank active auto refresh power down bank active suspend fig. 3 C state diagram (simplified for single bank operation state diagram) write write suspend power on precharge read write with auto precharge read with auto precharge writ read read writ bst bst mrs self selfx ref actv cke cke\(csus) cke cke read writ reada writa reada cke writa pre or pall pre or pall power applied definition of allows manual input automatic sequence writa reada pre or pall pre or pall cke\(pd) read suspend cke write suspend cke cke\(csus) cke\(csus) cke\(csus) cke\(csus) note: cke\ means cke goes low-level from high-level. 23 mb81f643242c-60/-70/-10 advanced info (ae0.1e) n bank operation command table minimum clock latency or delay time for 1 bank operation notes: *1. if t rp (min.) 26 mb81f643242c-60/-70/-10 advanced info (ae0.1e) n absolute maximum ratings (see warning) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions (referenced to v ss ) notes: warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. n capacitance (t a = 25 c, f = 1 mhz) parameter symbol value unit voltage of v cc supply relative to v ss v cc , v ccq C0.5 to +4.6 v voltage at any pin relative to v ss v in , v out C0.5 to +4.6 v short circuit output current i out 50 ma power dissipation p d 1.3 w storage temperature t stg C55 to +125 c parameter notes symbol min. typ. max. unit supply voltage v cc , v ccq 3.0 3.3 3.6 v v ss , v ssq 000v input high voltage *1 v ih 2.0 v cc + 0.5 v input low voltage *2 v il C0.5 0.8 v ambient temperature t a 070 c parameter symbol min. typ. max. unit input capacitance, except for clk c in1 2.5 5.0 pf input capacitance for clk c in2 2.5 4.0 pf i/o capacitance c i/o 4.0 6.5 pf *2. undershoot limit: v il (min.) 4.6v v ih v il pulse width 5 ns *1. overshoot limit: v ih (max.) 50% of pulse amplitude v ih v il -1.5v pulse width measured at 50% of pulse amplitude. = 4.6v for pulse width <= 5 ns acceptable, = v ss -1.5v for pulse width <= 5 ns acceptable, pulse width measured at 50% of pulse amplitude. 50% of pulse amplitude pulse width 5 ns v ih (min.) v il (max.) 27 mb81f643242c-60/-70/-10 advanced info (ae0.1e) n dc characteristics (at recommended operating conditions unless otherwise noted.) note *1, *2, and 3* (continued) parameter symbol condition value unit min. max. output high voltage v oh(dc) i oh = C2 ma 2.4 v output low voltage v ol(dc) i ol = 2 ma 0.4 v input leakage current (any input) i li 0 v v in v cc ; all other pins not under test = 0 v C5 5 m a output leakage current i lo 0 v v in v cc ; data out disabled C5 5 m a operating current (average power supply current) mb81f643242c-60 i cc1 burst: length = 1 t rc = min, t ck = min one bank active output pin open addresses changed up to 1-time during t rc (min) 0 v v in v il max v ih min v in v cc 165 ma MB81F643242C-70 155 mb81f643242c-10 115 reference value *4 @67mhz (cl=3) 100 precharge standby current (power supply current) i cc2p cke = v il all banks idle t ck = min power down mode 0 v v in v il max v ih min v in v cc 2ma i cc2ps cke = v il all banks idle clk = v ih or v il power down mode 0 v v in v il max v ih min v in v cc 1ma i cc2n cke = v ih all banks idle, t ck = 15 ns nop commands only, input signals (except to cmd) are changed 1 time during 30 ns 0 v v in v il max v ih min v in v cc 12ma i cc2ns cke = v ih all banks idle clk = v ih or v il input signal are stable 0 v v in v il max v ih min v in v cc 2ma 28 mb81f643242c-60/-70/-10 advanced info (ae0.1e) (continued) notes: *1. all voltage are referenced to v ss. *2. dc characteristics are measured after following the power-up initialization procedure in section n functional description. *3. i cc depends on the output termination or load conditions, clock cycle rate, signal clocking rate. the specified values are obtained with the output open and no termination register. *4. this value is for reference only. parameter symbol condition value unit min. max. active standby current (power supply current) i cc3p cke = v il any bank active t ck = min 0 v v in v il max v ih min v in v cc 2ma i cc3ps cke = v il any bank active clk = v ih or v il 0 v v in v il max v ih min v in v cc 1ma i cc3n cke = v ih any bank active t ck = 15 ns nop commands only, input signals (except to cmd) are changed 1 time during 30 ns 0 v v in v il max v ih min v in v cc 25ma i cc3ns cke = v ih any bank idle clk = v ih or v il input signals are stable 0 v v in v il max v ih min v in v cc 2ma burst mode current (average power supply current) mb81f643242c-60 i cc4 t ck = min burst length = 4 output pin open all banks active gapless data 0 v v in v il max v ih max v in v cc 305 ma MB81F643242C-70 260 mb81f643242c-10 185 reference value *4 @67mhz (cl=3) 125 refresh current #1 (average power supply current) mb81f643242c-60 i cc5 auto-refresh; t ck = min t rc = min 0 v v in v il max v ih max v in v cc 235 ma MB81F643242C-70 220 mb81f643242c-10 155 reference value *4 @67mhz (cl=3) 125 refresh current #2 (average power supply current) i cc6 self-refresh; t ck = min cke 0.2 v 0 v v in v il max v ih max v in v cc 2ma 29 mb81f643242c-60/-70/-10 advanced info (ae0.1e) n ac characteristics (at recommended operating conditions unless otherwise noted.) note *1, 2, and *3 parameter notes symbol mb81f643242c -60 mb81f643242c -70 mb81f643242c -10 reference value *4 @67mhz, cl=3 unit min. max. min. max. min. max. min. max. clock period cl = 2 t ck2 10 10 15 20 ns cl = 3 t ck3 6 7 10 15 ns clock high time *5 t ch 2.5 2.5 3 4 ns clock low time *5 t cl 2.5 2.5 3 4 ns input setup time *5 t si 1.522 3 ns input hold time *5 t hi 111 1 ns access time from clock (t ck = min) *5,*6, *7 cl = 2 t ac2 6 6 7 7ns cl = 3 t ac3 5.5 5.5 7 7 ns output in low-z *5 t lz 111 1 ns output in high-z *5,*8 cl = 2 t hz2 2.5 6 2.5 6 3 7 3 7ns cl = 3 t hz3 5.5 5.5 7 7 ns output hold time *5,*7 cl = 2 t oh 2.5 2.5 3 3 ns cl = 3 ns time between auto-refresh command interval *4 t refi 15.6 15.6 15.6 15.6 m s time between refresh t ref 64 64 64 64 ms transition time t t 0.5 10 0.5 10 0.5 10 0.5 10 ns cke setup time for power down exit time *5 t cksp 1.523 3 ns 30 mb81f643242c-60/-70/-10 advanced info (ae0.1e) base values for clock count/latency clock count formula note *10 parameter notes symbol mb81f643242c -60 mb81f643242c -70 mb81f643242c -10 reference value *4 @67mhz, cl=3 unit min. max. min. max. min. max. min. max. ras cycle time *9 t rc 60 63 90 110 ns ras precharge time t rp 18 20 30 40 ns ras active time t ras 42 110k 42 110k 60 110k 70 110k ns ras to cas delay time t rcd 18 20 30 30 ns write recovery time t wr 6 7 10 15 ns ras to ras bank active delay time t rrd 12 14 20 30 ns data-in to precharge lead time t dpl 7 7 10 15 ns data-in to active/ refresh command period cl=2 t dal2 1 cyc + t rp 1 cyc + t rp 1 cyc + t rp 1 cyc + t rp ns cl=3 t dal3 2 cyc + t rp 2 cyc + t rp 2 cyc + t rp 2 cyc + t rp ns mode resister set cycle time t rsc 12 14 20 30 ns clock 3 (round off a whole number) base value clock period 31 mb81f643242c-60/-70/-10 advanced info (ae0.1e) latency - fixed values (the latency values on these parameters are fixed regardless of clock period.) notes: *1. ac characteristics are measured after following the power-up initialization procedure in section n functional description. *2. ac characteristics assume t t = 1 ns and 30 pf of capacitive load. *3. 1.4 v is the reference level for measuring timing of input signals. transition times are measured between v ih (min) and v il (max). (see fig. 5) *4. this value is for reference only. *5. if input signal transition time (t t ) is longer than 1 ns; [(t t /2) C0.5] ns should be added to t ac (max), t hz (max), and t cksp (min) spec values, [(t t /2) C0.5] ns should be subtracted from t lz (min), t hz (min), and t oh (min) spec values, and (t t C1.0) ns should be added to t ch (min), t cl (min), t si (min), and t hi (min) spec values. *6. t ac also specifies the access time at burst mode. *7. t ac and t oh are the specs value under output load circuit shown in fig. 4. *8. specified where output buffer is no longer driven. *9. actual clock count of t rc (l rc ) will be sum of clock count of t ras (l ras ) and t rp (l rp ). *10. all base values are measured from the clock edge at the command input to the clock edge for the next command input. all clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number). parameter symbol mb81f643242c -60 mb81f643242c -70 mb81f643242c -10 unit cke to clock disable l cke 111cycle dqm to output in high-z l dqz 222cycle dqm to input data delay l dqd 000cycle last output to write command delay l owd 222cycle write command to input data delay l dwd 000cycle precharge to outputing high-z delay cl = 2 l roh2 222cycle cl = 3 l roh3 333cycle burst stop command to output in high-z delay cl = 2 l bsh2 222cycle cl = 3 l bsh3 333cycle cas to cas delay (min) l ccd 111cycle cas bank delay (min) l cbd 1 1 1 cycle 32 mb81f643242c-60/-70/-10 advanced info (ae0.1e) output note: by adding appropriate correlation factors to the test conditions, t ac and t oh measured when the output is coupled to the output load circuit are within specifications. fig. 4 C output load circuit r 1 = 50 w cl = 30 pf lvttl 1.4 v 33 mb81f643242c-60/-70/-10 advanced info (ae0.1e) t si t hi t ch t ck t ac t hz t oh t lz t cl clk input (control, addr. & data) output 2.4 v 1.4 v 0.4 v 1.4 v 2.4 v 0.4 v 1.4 v 2.4 v 0.4 v note: reference level of input signal is 1.4 v for lvttl. access time is measured at 1.4 v for lvttl. fig. 5 C timing diagram, setup, hold and delay time clk cke t cksp (min) nop dont care dont care command 1 clock (min) nop actv fig. 6 C timing diagram, delay time for power down exit 34 mb81f643242c-60/-70/-10 advanced info (ae0.1e) fig. 7 C timing diagram, pulse width t rc , t rp , t ras , t rcd , t wr , t ref , t dpl , t dal , t rsc , t rrd , t cksp command command clk input (control) note: these parameters are a limit value of the rising edge of the clock from one command input to next input. t cksp is the latency value from the rising edge of cke. measurement reference voltage is 1.4 v. fig. 8 C timing diagram, access time t ac (cas latency C 1) t ck clk command dq 0 to dq 31 (output) q(valid) read t ac q(valid) q(valid) t ac 35 mb81f643242c-60/-70/-10 advanced info (ae0.1e) n timing diagrams timing diagram C 1 : clock enable - read and write suspend (@ bl = 4) q1 q2 (no change) q3 (no change) q4 d1 not written d2 not written d3 d4 clk cke clk (internal) dq 0 to dq 31 (read) dq 0 to dq 31 (write) notes: *1. the latency of cke (l cke ) is one clock. *2. during read mode, burst counter will not be incremented/decremented at the next clock of csus command. output data remain the same data. *3. during the write mode, data at the next clock of csus command is ignored. *1 *3 *3 *1 *2 *2 *2 *2 i cke (1 clock) i cke (1 clock) timing diagram C 2 : clock enable - power down entry and exit nop pd(nop) dont care nop actv clk cke command 1 clock (min) *1 *2 *3 nop *3 notes: *1. precharge command (pre or pall) should be asserted if any bank is active and in the burst mode. *2. precharge command can be posted in conjunction with cke after the last read data have been appeared on dq. *3. it is recommended to apply nop command in conjunction with cke. *4. the actv command can be latched after t cksp (min) + 1 clock (min). t cksp (min) t ref (max) *4 36 mb81f643242c-60/-70/-10 advanced info (ae0.1e) timing diagram C 3 : column address to column address input delay clk ras cas row address column address address i ccd (1 clock) t rcd (min) note: cas to cas delay can be one or more clock period. i ccd i ccd i ccd column address column address column address column address timing diagram C 4 : different bank address input delay t rrd (min) clk ras cas row address address bank 0 bank 3 bank 3 bank 3 bank 0 bank 0 ba 0 , ba 1 t rcd (min) i cbd (1 clock) i cbd column address row address column address column address column address t rcd (min) or more note: cas bank delay can be one or more clock period. 37 mb81f643242c-60/-70/-10 advanced info (ae0.1e) timing diagram C 5 : dqm 0 - dqm 3 - input mask and output disable (@ bl = 4) clk dqm 0 to dqm 3 (@ read) dq 0 to dq 31 (@ read) dqm 0 to dqm 3 (@ write) dq 0 to dq 31 (@ write) q1 q2 hi-z q4 end of burst d1 masked d3 d4 end of burst i dqz (2 clocks) i dqd (same clock) timing diagram C 6 : precharge timing (applied to the same bank) t ras (min) clk command actv pre note: precharge means pre or pall. 38 mb81f643242c-60/-70/-10 advanced info (ae0.1e) timing diagram C 7 : read interrupted by precharge (example @ cl = 2, bl = 4) clk command dq 0 to dq 31 command dq 0 to dq 31 command dq 0 to dq 31 command dq 0 to dq 31 hi-z q1 precharge q1 q2 q1 q2 q3 q1 q2 q3 q4 hi-z hi-z no effect (end of burst) note: in case of cl = 2, the l roh is 2 clocks. in case of cl = 3, the l roh is 3 clocks. precharge means pre or pall. i roh (2 clocks) i roh (2 clocks) i roh (2 clocks) precharge precharge precharge 39 mb81f643242c-60/-70/-10 advanced info (ae0.1e) timing diagram C 8 : read interrupted by burst stop (example @ bl = full column) clk command (cl = 2) dq 0 to dq 31 command (cl = 3) dq 0 to dq 31 q n q n+1 hi-z hi-z q n+2 q n-1 q n-2 q n q n+1 q nC1 q nC2 l bsh (2 clocks) l bsh (3 clocks) bst bst timing diagram C 9 : write interrupted by burst stop (example @ bl = 2) clk command dq 0 to dq 31 last data-in masked by bst bst command 40 mb81f643242c-60/-70/-10 advanced info (ae0.1e) timing diagram C 10 : write interrupted by precharge (example @ cl = 3) t rp (min) t dpl (min) clk command dq 0 to dq 31 actv data- last data-in masked by precharge note: the precharge command (pre) should only be issued after the t dpl of final data input is satisfied. precharge means pre or pall. precharge timing diagram C 11 : read interrupted by write (example @ cl = 3, bl = 4) clk command dqm (dqm 0 to dqm 3 ) dq 0 to dq 31 q 1 masked d 1 d 2 *1 *2 *3 writ notes: *1. first dqm makes high-impedance state high-z between last output and first input data. *2. second dqm makes internal output data mask to avoid bus contention. *3. third dqm in illustrated above also makes internal output data mask. if burst read ends (final data output) at or after the second clock of burst write, this third dqm is required to avoid internal bus contention. i dwd (same clock) i owd (2 clocks) i dqz (2 clocks) read 41 mb81f643242c-60/-70/-10 advanced info (ae0.1e) timing diagram C 12 : write to read timing (example @ cl = 3, bl = 4) clk command dq 0 to dq 31 dqm (dqm 0 to dqm 3 ) note: read command should be issued after t wr of final data input is satisfied. writ read d1 q1 q2 d3 masked by read t wr (min) d2 (cl-1) t ck t ac (max) 42 mb81f643242c-60/-70/-10 advanced info (ae0.1e) reada actv nop or desl actv q1 q2 t ras (min) 2 clocks (same value as bl) t rp (min) timing diagram C 13 : read with auto-precharge (example @ cl = 2, bl = 2 applied to same bank) clk command dqm (dqm 0 to dqm 3 ) dq 0 to dq 31 notes: *1. precharge at read with auto-precharge command (reada) is started from number of clocks that is the same as burst length (bl) after the reada command is asserted. *2. next actv command should be issued after bl+t rp (min) from reada command. bl+t rp (min) *1 *2 writa actv actv d1 d2 t dal (min) timing diagram C 14 : write with auto-precharge *1, *2, and *3 (example @ cl = 2, bl = 2 applied to same bank) clk command dqm (dqm 0 to dqm 3 ) dq 0 to dq 31 nop or desl notes: *1. even if the final data is masked by dqm, the precharge does not start the clock of final data input. *2. once auto precharge command is asserted, no new command within the same bank can be issued. *3. auto-precharge command doesnt affect at full column burst operation except burst read & single write. *4. precharge at write with auto-precharge is started after the cl - 1 from the end of burst. *5. next command should be issued after bl+ t rp (min) at cl = 2, bl+1+t rp (min) at cl = 3 from writa command. t ras (min) bl+t rp (min) cl- 1 *4 *5 43 mb81f643242c-60/-70/-10 advanced info (ae0.1e) timing diagram C 15 : auto-refresh timing t rc (min) t rc (min) clk command ba 0 , ba 1 ref command nop ba *1 nop nop ref nop *4 dont care notes: *1. all banks should be precharged prior to the first auto-refresh command (ref). *2. bank select is ignored at ref command. the refresh address and bank select are selected by internal refresh counter. *3. either nop or desl command should be asserted during t rc period while auto-refresh mode. *4. any activation command such as actv or mrs command other than ref command should be asserted after t rc from the last ref command. *3 dont care *3 *3 *3 *2 *2 timing diagram C 16 : self-refresh entry and exit timing t rc (min) t cksp (min) clk cke command nop notes: *1. precharge command (pre or pall) should be asserted if any bank is active prior to self-refresh entry command (self). *2. the self-refresh exit command (selfx) is latched after t cksp (min). it is recommended to apply nop command in conjunction with cke. *3. either nop or desl command can be used during t rc period. *4. cke should be held high within one t rc period after t cksp . self dont care selfx command nop *2 nop *3 *1 t si (min) *4 44 mb81f643242c-60/-70/-10 advanced info (ae0.1e) timing diagram C 17 : mode register set timing clk command address mrs nop or desl mode row address actv notes: the mode register set command (mrs) should only be asserted after all banks have been precharged. t rsc (min) 45 mb81f643242c-60/-70/-10 advanced info (ae0.1e) n scitt test mode about scitt scitt (static component interconnection test technology) is an xnor circuit based test technology that is used for testing interconnection between sdram and sdram controller on the printed circuit boards. scitt provides inexpensive board level test mode in combination with boundary-scan. the basic idea is simple, consider all output of sdram as output of xnor circuit and each output pin has a unique mapping on the input of sdram. the ideal schematic block diagram is as shown below. it is static and provides easy test pattern that result in a high diagnostic resolution for detecting all open/short faults. the mb81f643242c adopts scitt as an optional function. see package and ordering information in section n package. m c asic sdram controller test control xaddress bus data bus sdram core xnor boundary scan test control : cas, cs , cke xaddress bus : a 0 to a 10 , ba 0 , ba 1 , ras , dqm 0 to dqm 3 , clk, we data bus : dq 0 to dq 31 46 mb81f643242c-60/-70/-10 advanced info (ae0.1e) scitt test sequence the followings are the scitt test sequence. scitt test can be executed after power-on and prior to precharge command in power-up initialization. once precharge command is issued to sdram, it never get back to scitt test mode during regular operation for the purpose of a fail-safe way in get in and out of test mode. 1. apply power. attempt to maintain either nop or desl command at the input. 2. maintain stable power for a minimum of 100us. 3. enter scitt test mode. 4. execute scitt test. 5. exit from scitt mode. it is required to follow power on sequence to execute read or write operation. 6. start clock. attempt to maintain either nop or desl command at the input. 7. precharge all banks by precharge (pre) or precharge all command (pall). 8. assert minimum of 2 auto-refresh command (ref). 9. program the mode register by mode register set command (mrs). the 3,4,5 steps define the scitt mode available. it is possible to skip these steps if necessary (refer to power- up initialization). command truth table note *1 notes: *1. l = logic low, h = logic high, v = valid, x = either l or h *2. the scitt mode entry command assumes the first cas falling edge with cs and cke = l after power on. *3. the scitt mode exit command assumes the first cas rising edge after the test mode entry. *4. refer the test code table. *5. cs = h or cke = l is necessary to disable outputs in scitt mode exit. control input output cas cs cke we ras a 0 to a 10 ba 0 , ba 1 dqm 0 to dqm 3 clk dq 0 to dq 31 scitt mode entry h ? l * 2 llxxxx xx scitt mode exit l ? h * 3 h *5 l *5 xxxxxx scitt mode output enable * 4 llhvvvvvv 47 mb81f643242c-60/-70/-10 advanced info (ae0.1e) test code table dq 0 to dq 31 output data is static and is determined by following logic during the scitt mode operation. dq 0 = ras xnor a 0 dq 1 = ras xnor a 1 dq 2 = ras xnor a 2 dq 3 = ras xnor a 3 dq 4 = ras xnor a 4 dq 5 = ras xnor a 5 dq 6 = ras xnor a 6 dq 7 = ras xnor a 7 dq 8 = ras xnor a 8 dq 9 = ras xnor a 9 dq 10 = ras xnor a 10 dq 11 = ras xnor ba 1 dq 12 = ras xnor ba 0 dq 13 = ras xnor dqm 0 dq 14 = ras xnor dqm 1 dq 15 = ras xnor dqm 2 dq 16 = ras xnor dqm 3 dq 17 = ras xnor clk dq 18 = ras xnor we dq 19 = a 0 xnor a 1 dq 20 = a 0 xnor a 2 dq 21 = a 0 xnor a 3 dq 22 = a 0 xnor a 4 dq 23 = a 0 xnor a 5 dq 24 = a 0 xnor a 6 dq 25 = a 0 xnor a 7 dq 26 = a 0 xnor a 8 dq 27 = a 0 xnor a 9 dq 28 = a 0 xnor a 10 dq 29 = a 0 xnor ba 1 dq 30 = a 0 xnor ba 0 dq 31 = a 0 xnor dqm 0 ? example of test code table input bus output bus 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 h l l h h h h h h h h h h h h h h h h h h l l h h h h h h h h h h h h h h h h h h h h l h l h h h h h h h h h h h h h h h h h l h l h h h h h h h h h h h h h h h h h h h l h h l h h h h h h h h h h h h h h h h l h h l h h h h h h h h h h h h h h h h h h l h h h l h h h h h h h h h h h h h h h l h h h l h h h h h h h h h h h h h h h h h l h h h h l h h h h h h h h h h h h h h l h h h h l h h h h h h h h h h h h h h h h l h h h h h l h h h h h h h h h h h h h l h h h h h l h h h h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h h h h l h h h h h l h h h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h h h h l h h h h l h h h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h h h h l h h h l h h h h h h h h h h h h h h h l h h h h h l h h h h h h h h h h h h h h h h l h h l h h h h h h h h h h h h h h h h l h h h h l h h h h h h h h h h h h h h h h h l h l h h h h h h h h h h h h h h h h h l h h h l h h h h h h h h h h h h h h h h h h l l h h h h h h h h h h h h h h h h h h l h h h l l h h h h h h h h h h h h h h h h h h l l h h h h h h h h h h h h h h h h h h h h l h l h h h h h h h h h h h h h h h h h l h l h h h h h h h h h h h h h h h h h h h l h h l h h h h h h h h h h h h h h h h l h h l h h h h h h h h h h h h h h h h h h l h h h l h h h h h h h h h h h h h h h l h h h l h h h h h h h h h h h h h h h h h l h h h h l h h h h h h h h h h h h h h l h h h h l h h h h h h h h h h h h h h h h l h h h h h l h h h h h h h h h h h h h l h h h h h l h h h h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h l h h h h h h ras a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 ba 1 ba 0 dqm 0 dqm 1 dqm 2 dqm 3 clk we dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 16 dq 17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 0 = input low, 1 = input high, l = output low, h = output high 48 mb81f643242c-60/-70/-10 advanced info (ae0.1e) ac specification timing diagrams parameter description minimum maximum units t ts test mode entry set up time 10 ns t th test mode entry hold time 10 ns t epd test mode exit to power on sequence delay time 10 ns t tlz test mode output in low-z time 0 ns t thz test mode output in high-z time 0 20 ns t tca test mode access time from control signals (output enable & chip select) 40ns t tia test mode input access time 20 ns t toh test mode output hold time 0 ns t etd test mode entry to test delay time 10 ns t tih test mode input hold time 30 ns timing diagram C 1 : power-up timing diagram v dd cs cke cas *3 100 m s pause time test mode entry point notes: *1. scitt is enabled if cs = l, cke = l, cas = l at just power on. *2. all output buffers maintains in high-z state regardless of the state of control signals as long as the above timing is maintained. *3. cas must not be brought from high to low. *2 *1 49 mb81f643242c-60/-70/-10 advanced info (ae0.1e) timing diagram C 2 : scitt test entry and exit *1 t ts v cc cas cs cke t th entry exit pause 100 m s l l next power on sequence and normal operation h ? l notes: *1. if entry and exit operation have not been done correctly, cas , cs , cke pins will have some problems. *2. pre or pall commands must not be asserted. test mode is disable by those commands. *3. outputs must be disabled by cs = h or cke = l before exit. *2 *3 test mode t epd 50 mb81f643242c-60/-70/-10 advanced info (ae0.1e) timing diagram C 3 : output control (1) v dd cas cs cke t tlz entry dq turn to low-z at cs =l and cke=h dq 0 to dq 31 t thz dq turn to high-z at cs =h cas must not brought from high to low high-z high-z high-z low-z time (a) time (b) time (c) memory device output buffer status this is not bus line level timing diagram C 4 : output control (2) v dd cas cs cke t tlz entry dq turn to low-z at cs =l and cke=h dq 0 to dq 31 t thz cas must not brought from high to low high-z high-z high-z low-z time (a) time (b) time (c) memory device output buffer status this is not bus line level dq turn to high-z at cke=l 51 mb81f643242c-60/-70/-10 advanced info (ae0.1e) timing diagram C 5 : test timing (1) cs cke t etd test mode entry command test mode entry dq becomes low-z at cs =l and cke=h t tca t tia t tia t tia t tlz t toh t toh valid valid valid a 0 a 1 a 2 dq 0 to dq 31 under check pins under test cas 52 mb81f643242c-60/-70/-10 advanced info (ae0.1e) timing diagram C 6 : test timing (2) cs -#1 cke test mode entry t tia t toh valid a 0 a 1 a 2 dq 0 to dq 31 under check pins test mode exit under test cas cs -#2 valid valid valid valid t tia t tia t toh t thz t tlz t tia t tca t tih t tia t toh t tih t tih tested #1 device tested #2 device changed under test devices l l h 53 mb81f643242c-60/-70/-10 advanced info (ae0.1e) timing diagram C 7 : test timing (3) cs -#1 cke test mode entry t tia t toh valid a 0 a 1 a 2 dq 0 to dq 31 under check pins test mode exit under test cas cs -#2 valid valid valid valid t tia t tia t toh t thz t tlz t tia t tca t tih t tia t toh t tih t tih tested #1 device tested #2 device changed under test devices l l h 54 mb81f643242c-60/-70/-10 advanced info (ae0.1e) n package dimension c 1996 fujitsu limited f86001s-1c-1 0.45/0.75 (.018/.030) 0~8? 0.25(.010) details of "a" part 86 44 43 1 lead no. index .009 ?.002 +.002 ?0.04 +0.05 0.22 m 0.10(.004) 22.220.10(.875.004) * 0.50(.020)typ 0.10(.004) 21.00(.827)ref 0.100.05 (.004.002) (stand off) 1.20(.047)max .006 ?.001 +.002 ?0.03 +0.05 0.145 10.160.10(.400.004) 11.760.20(.463.008) "a" (mounting height) dimensions in mm (inches) 86-pin plastic tsop(ii) (fpt-86p-m01) *: resin protrusion. (each side: 0.15 (.006) max) 55 mb81f643242c-60/-70/-10 advanced info (ae0.1e) memo 56 mb81f643242c-60/-70/-10 advanced info (ae0.1e) fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f0001 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inhereut chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. |
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